SpaceWire to SPI Bridge in VHDL for Microsemi ProASIC3E FPGA

Author: 

Andrei Maalberg

Degree: 

M.Sc.

Supervisors: 

Date: 

Tuesday, June 5, 2018

Thesis language: 

English

Abstract: 

Even though digital designs incorporating a system-on-a-chip (SoC) architecture are becoming increasingly prevalent nowadays, there are still certain applications, e.g. space industry projects, where the rise of the system complexity caused by the use of SoC architectures may not be always justified. This work addresses this issue by designing a lean hardware-only solution for its final goal—a SpaceWire to SPI bridge developed in cooperation with the Space Exploration Institute (Space-X). By analyzing the possible design architecture options, including the one based on SoC, this work provides critical arguments regarding the choice of the hardware-only architecture. Additionally, while targeting ProASIC3E FPGA from Microsemi this work gives the required overview of both the educational and technical resources provided by this FPGA vendor. Based on the positive results of the final design implementation, this work has shown that a hardware-only design approach is indeed a viable architecture solution even if it may take more time to be developed compared to SoC design. Finally, the design solution proposed in this work could be especially attractive for the other projects that require this kind of communication bridge functionality while facing similar design architecture constraints.

Electronic version: 

Note: 

This work received the main prize as well as a special prize from AS Cybernetica in the ICT thesis contest of 2018 in the M.Sc. Hardware and Systems category.

Co-supervised with René Beuchat (EPFL), Jean-Luc Josset (Space-X) and Mitko Tanevski (Space-X).